In many practical applications involving electrical circuits in MOS technology, such as MOS memory and logic circuits, it is desired to have an on-chip MOS circuit for multiplying or "boosting" an applied external voltage. In prior art, such voltage multiplier circuits have taken such forms as "Jacobs ladders" (see, for example, John Markus, Electronic Circuits Manual, p. 139: "DC Voltage Converter"), as well as circuits in which capacitors are alternately connected in parallel and series, an external voltage being applied to each capacitor during the parallel connection phase (see, for example, L. M. Braslavskii et al., "Means of Transformerless Voltage Conversion and Construction of Transformerless Secondary Power Sources", Instruments and Experimental Techniques, Vol. 20. No. 4, pp. 1132-1140, at pp. 1138-1139). However, these prior art techniques suffer from undesirable threshold voltage drops across the various MOS diodes used in these circuits, thereby undesirably reducing the amount of voltage multiplication or, conversely, undesirably increasing the required number of capacitors and hence the required semiconductor chip area for a given desired voltage output, as well as causing undesirable power loss. It would therefore be desirable to have a voltage multiplier circuit in MOS technology which alleviates this problem.
In accordance with the invention, a stage (FIG. 1) of a voltage converter circuit includes a capacitor (C.sub.1) having a pair of terminals each of which is connected through the source drain path of a separate MOS transistor switch (M.sub.3, M.sub.5) to a separate first and second voltage source terminal (ground, V.sub.1) for alternately connecting and disconnecting said capacitor (C.sub.1) to said first and second voltage source terminals (ground, V.sub.1), one terminal of a capacitor (C.sub.1) being also connected through the source-drain path of series-connected MOS transistor (M.sub.1) to a second voltage source terminal (V.sub.2), the gate electrode of said series-connected transistor (M.sub.1) being connected to another MOS transistor switch (M.sub.4) for alternately turning "on" and "off" said series-connected transistor (M.sub.1), CHARACTERIZED IN THAT said circuit further includes a feedback loop running from the other terminal of said capacitor C.sub.1 through a load (M.sub.2) back to the gate electrode of said series connected MOS transistor (M.sub.1). This load (M.sub.2) advantageously is formed by the source-drain path of an MOS transistor whose gate electrode is connected through the source-drain path of MOS transistor switch (M.sub.6) to a voltage source terminal and to one terminal of a second, smaller capacitor (C.sub.2) having another terminal which is connected to the gate electrode of the series-connected transistor (M.sub.1). Since it is the capacitor C.sub.1 which consumes most of the semiconductor wafer area, the extra area consumed by the added elements of this invention is more than compensated by the higher output voltage, especially in multistage embodiments (FIG. 3) of this invention.